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rt8010/a 1 ds8010/a-02 march 2007 www.richtek.com features +2.5v to +5.5v input range output voltage (adjustable output from 0.6v to v in ) ` ` ` ` ` rt8010 : 1.0v, 1.2v, 1.5v, 1.6v, 1.8v, 2.5v and 3.3v fixed/adjustable output voltage ` ` ` ` ` rt8010a adjustable output voltage only 1a output current 95% efficiency no schottky diode required 1.5mhz fixed-frequency pwm operation small 6-lead wdfn and 16-lead wqfn package rohs compliant and 100% lead (pb)-free applications mobile phones personal information appliances wireless and dsl modems mp3 players portable instruments 1.5mhz, 1a, high efficiency pwm step-down dc/dc converter general description the rt8010/a is a high-efficiency pulse-width-modulated (pwm) step-down dc-dc converter. capable of delivering 1a output current over a wide input voltage range from 2.5v to 5.5v, the rt8010/a is ideally suited for portable electronic devices that are powered from 1-cell li-ion battery or from other power sources such as cellular phones, pdas and hand-held devices. two operating modes are available including : pwm/low- dropout autoswitch and shut-down modes. the internal synchronous rectifier with low r ds(on) dramatically reduces conduction loss at pwm mode. no external schottky diode is required in practical application. the rt8010/a enters low-dropout mode when normal pwm cannot provide regulated output voltage by continuously turning on the upper pmos. rt8010/a enter shut-down mode and consumes less than 0.1 a when en pin is pulled low. the switching ripple is easily smoothed-out by small package filtering elements due to a fixed operating frequency of 1.5mhz. this along with small wdfn-6l 2x2 and wqfn-16l 3x3 package provides small pcb area application. other features include soft start, lower internal reference voltage with 2% accuracy, over temperature protection, and over current protection. note : richtek pb-free and green products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. ` 100% matte tin (sn) plating. ordering information pin configurations (top view) wdfn-6l 2x2 (rt8010) marking information for marking information, contact our sales representative directly or through a richtek distributor located in your area, otherwise visit our website for detail. 12 11 10 9 13 14 15 16 1 2 3 4 8 7 6 5 fb/vout gnd gnd gnd vin vin vin vin gnd en nc nc nc lx lx lx nc vin fb/vout gnd lx en 5 4 1 2 3 6 wqfn-16l 3x3 (rt8010a) rt8010/a(- ) package type qw : wdfn/wqfn (w-type) operating temperature range p : pb free with commercial standard g : green (halogen free with commer- cial standard) output voltage default : adjustable (rt8010/a) fixed (rt8010) 10 : 1.0v 12 : 1.2v 15 : 1.5v 16 : 1.6v 18 : 1.8v 25 : 2.5v 33 : 3.3v wqfn-16l 3x3 wdfn-6l 2x2
rt8010/a 2 ds8010/a-02 march 2007 www.richtek.com typical application circuit figure 1. fixed voltage regulator figure 2. adjustable voltage regulator ? ? ? ? ? ? + = r2 r1 1 x v v ref out with r2 = 300k to 60k so the i r2 = 2 a to 10 a, and (r1 x c1) should be in the range between 3x10 -6 and 6x10 -6 for component selection. figure 3 layout note: 1. the distance that c in connects to v in is as close as possible (under 2mm). 2. c out should be placed near rt8010/a. layout guide 4.7uf 10uf vin lx nc rt8010/a en vout 2.2uh 2.5v to 5.5v v in v out c in l 6 4 3 2 5 c out gnd 1 4.7uf 10uf vin lx rt8010/a en fb 2.2uh 2.5v to 5.5v v in v out c in l 6 4 3 2 c out r1 r2 c1 i r2 nc 5 gnd 1 nc en vin fb gnd lx rt8010/a_adj c in must be placed between v dd and gnd as closer as possible lx should be connected to inductor by wide and short trace, keep sensitive compontents away from this trace output capacitor must be near rt8010/a l1 c out c in 1 2 3 4 5 6 r1 r2 l1 nc en vin gnd lx c out c in rt8010/a_fix c in must be placed between v dd and gnd as closer as possible lx should be connected to inductor by wide and short trace, keep sensitive compontents away from this trace output capacitor must be near rt8010 1 2 3 4 5 6 vout
rt8010/a 3 ds8010/a-02 march 2007 www.richtek.com function block diagram functional pin description pin number pin name pin function rt8010 rt8010a 1, exposed pad 6, 8, 16, exposed pad nc no internal connect (floating or connecting to gnd). 2 7 en chip enable (active high). 3 9, 10, 11, 12 vin power input. (pin 9 and pin 10 must be connected with pin 11) 4 13, 14, 15 lx pin for switching. (pin 13 must be connected with pin 14) 5 1, 2, 3, 5 gnd ground. 6 4 fb/vout feedback/output voltage pin. comp rc rs1 rs2 en vin lx fb/vout uvlo & power good detector v ref slope compensation current sense osc & shutdown control current limit detector driver control logic pwm comparator error amplifier gnd
rt8010/a 4 ds8010/a-02 march 2007 www.richtek.com absolute maximum ratings (note 1) supply input v oltage ------------------------------------------------------------------------------------------------------ 6.5v en, fb pin voltage ------------------------------------------------------------------------------------------------------- ? 0.3v to v in power dissipation, p d @ t a = 25 c wdfn-6l 2x2 -------------------------------------------------------------------------------------------------------------- 0.606w wqfn-16l 3x3 ------------------------------------------------------------------------------------------------------------ 1.47w package thermal resistance (note 4) wdfn-6l 2x2, ja --------------------------------------------------------------------------------------------------------- 165 c/w wdfn-6l 2x2, jc -------------------------------------------------------------------------------------------------------- 20 c/w wqfn-16l 3x3, ja ------------------------------------------------------------------------------------------------------- 68 c/w wqfn-16l 3x3, jc ------------------------------------------------------------------------------------------------------ 7.5 c/w lead temperature (soldering, 10 se c.) ------------------------------------------------------------------------------- 260 c storage temperature range -------------------------------------------------------------------------------------------- ? 65 c to 150 c junction temperature ----------------------------------------------------------------------------------------------------- 150 c esd susceptibility (note 2) hbm (human body mode) ---------------------------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------------------------ 200v electrical characteristics (v in = 3.6v, v out = 2.5v, v ref = 0.6v, l = 2.2 h, c in = 4.7 f, c out = 10 f, t a = 25 c, i max = 1a unless otherwise specified) parameter symbol test conditions min typ max units input voltage range v in 2.5 -- 5.5 v quiescent current i q i out = 0ma, v fb = v ref + 5% -- 50 70 a shutdown current i shdn en = gnd -- 0.1 1 a reference voltage v ref for adjustable output voltage 0.588 0.6 0.612 v adjustable output range v out (note 6) v ref -- v in ? 0.2v v v out v in = 2.5v to 5.5v, v out = 1.0v 0a < i out < 1a ? 3 -- +3 % v out v in = 2.5v to 5.5v, v out = 1.2v 0a < i out < 1a ? 3 -- +3 % v out v in = 2.5v to 5.5v, v out = 1.5v 0a < i out < 1a ? 3 -- +3 % v out v in = 2.5v to 5.5v, v out = 1.6v 0a < i out < 1a ? 3 -- +3 % output voltage accuracy fix v out v in = 2.5v to 5.5v, v out = 1.8v 0a < i out < 1a ? 3 -- +3 % to be continued recommended operating conditions (note 3) supply input v oltage ------------------------------------------------------------------------------------------------------ 2.5v to 5.5v junction temperature range -------------------------------------------------------------------------------------------- ? 40 c to 125 c ambient temperature range -------------------------------------------------------------------------------------------- ? 40 c to 85 c
rt8010/a 5 ds8010/a-02 march 2007 www.richtek.com parameter symbol test conditions min typ max units v out v in = v out + v to 5.5v (note 5) ? 3 -- +3 % output voltage accuracy fix v out v in = v out + v to 5.5v (note 5) ? 3 -- +3 % output voltage accuracy adjustable v out v in = v out + v to 5.5v (note 5) 0a < i out < 1a ? 3 -- +3 % fb input current i fb v fb = v in ? 50 -- 50 na v in = 3.6v -- 0.28 -- pmosfet r on r ds(on)_p i out = 200ma v in = 2.5v -- 0.38 -- v in = 3.6v -- 0.25 -- nmosfet r on r ds(on)_n i out = 200ma v in = 2.5v -- 0.35 -- p-channel current limit i lim_p v in = 2.5v to 5.5 v 1.4 1.5 -- a en high-level input voltage v en_h v in = 2.5v to 5.5v 1.5 -- -- en low-level input voltage v en_l v in = 2.5v to 5.5v -- -- 0.4 v under voltage lock out threshold uvlo -- 1.8 -- v hysteresis -- 0.1 -- v oscillator frequency f osc v in = 3.6v, i out = 100ma 1.2 1.5 1.8 mhz thermal shutdown temperature t sd -- 160 -- c max. duty cycle 100 -- -- % lx leakage current v in = 3.6v, v lx = 0v or v lx = 3.6v ? 1 -- 1 a note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. the device is not guaranteed to function outside its operating conditions. note 4. ja is measured in the natural convection at t a = 25 c on a high effective four layers thermal conductivity test board of jedec 51-7 thermal measurement standard. the case point of jc is on the expose pad for the qfn package. note 5. v = i out x p rds(on) note 6. guarantee by design.
rt8010/a 6 ds8010/a-02 march 2007 www.richtek.com typical operating characteristics efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 output current (a) efficiency (%) v out = 3.3v, c out = 4.7 f, l = 4.7 h v in = 3.6v v in = 4.2v v in = 5.0v efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 output current (a) efficiency (%) v out = 1.2v, c out = 10 f, l = 2.2 h v in = 5.0v v in = 3.3v v in = 2.5v efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 output current (a) efficiency (%) v out = 1.2v, c out = 4.7 f, l = 4.7 h v in = 5.0v v in = 3.3v v in = 2.5v uvlo voltage vs.temperature 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature input voltage (v) ( c) v out = 1.2v, i out = 0a rising falling en pin threshold vs. input voltage 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 input voltage (v) en pin threshold (v) v out = 1.2v, i out = 0a rising falling en pin threshold vs. temperature 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature en pin threshold (v) v in = 3.6v, v out = 1.2v, i out = 0a rising falling ( c)
rt8010/a 7 ds8010/a-02 march 2007 www.richtek.com output voltage vs. temperature 1.15 1.16 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1.24 1.25 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature output voltage (v) v in = 3.6v, i out = 0a ( c) output current limit vs. input voltage 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 input voltage (v) output current limit (a) v out = 1.2v @ t a = 20 c output current limit vs. temperature 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature output current limit (a) v in = 5.0v v in = 3.6v v in = 3.3v ( c) v out = 1.2v frequency vs. temperature 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature frequency (khz) v in = 3.6v, v out = 1.2v, i out = 300ma ( c) frequency vs. input voltage 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 input voltage (v) frequency (khz) v in = 3.6v, v out = 1.2v, i out = 300ma output voltage vs. load current 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 1.225 1.230 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 load current (a) output voltage (v) v in = 5.0v v in = 3.6v
rt8010/a 8 ds8010/a-02 march 2007 www.richtek.com power on from en time (100 s/div) v in = 3.6v, v out = 1.2v, i out = 10ma v out (1v/div) v en (2v/div) i in (500ma/div) power on from en time (100 s/div) v in = 3.6v, v out = 1.2v, i out = 1a v out (1v/div) v en (2v/div) i in (500ma/div) power off from en time (100 s/div) v in = 3.6v, v out = 1.2v, i lx = 1a v out (1v/div) v en (2v/div) i lx (1a/div) power on from vin time (250 s/div) v en = 3v, v out = 1.2v, i lx = 1a v out (1v/div) v in (2v/div) i lx (1a/div) load transient response time (50 s/div) v in = 3.6v, v out = 1.2v i out = 50ma to 1a v out ac (50mv/div) i out (500ma/div) load transient response time (50 s/div) v in = 3.6v, v out = 1.2v i out = 50ma to 0.5a v out ac (50mv/div) i out (500ma/div)
rt8010/a 9 ds8010/a-02 march 2007 www.richtek.com load transient response time (50 s/div) v in = 5v, v out = 1.2v i out = 50ma to 1a v out ac (50mv/div) i out (500ma/div) output ripple voltage time (500ns/div) v in = 3.6v, v out = 1.2v i out = 1a v out (10mv/div) v lx (2v/div) output ripple voltage time (500ns/div) v in = 5v, v out = 1.2v i out = 1a v out (10mv/div) v lx (2v/div) load transient response time (50 s/div) v in = 5v, v out = 1.2v i out = 50ma to 0.5a v out ac (50mv/div) i out (500ma/div)
rt8010/a 10 ds8010/a-02 march 2007 www.richtek.com ? ? ? ? ? ? + out l out 8fc 1 esr i v applications information the basic rt8010/a application circuit is shown in typical application circuit. external component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by c in and c out . inductor selection for a given input and output voltage, the inductor value and operating frequency determine the ripple current. the ripple current i l increases with higher v in and decreases with higher inductance. having a lower ripple current reduces the esr losses in the output capacitors and the output voltage ripple. highest efficiency operation is achieved at low frequency with small ripple current. this, however, requires a large inductor. a reasonable starting point for selecting the ripple current is i l = 0.4(i max ). the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or mollypermalloy cores. actual core loss is independent of core size for a fixed inductor value but it is very dependent on the inductance selected. as the inductance increases, core losses decrease. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates ? hard ? , which means that inductance collapses abruptly when the peak design ? ? ? ? ? ? ? ? ? ? ? ? ? = in out out l v v 1 l f v i ? ? ? ? ? ? ? ? ? ? ? ? ? = in(max) out l(max) out v v 1 i f v l current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate energy but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price vs size requirements and any radiated field/emi requirements. c in and c out selection the input capacitance, c in , is needed to filter the trapezoidal current at the source of the top mosfet. to prevent large ripple voltage, a low esr input capacitor sized for the maximum rms current should be used. rms current is given by : 1 v v v v i i out in in out out(max) rms ? = this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, v out , is determined by :
rt8010/a 11 ds8010/a-02 march 2007 www.richtek.com the output ripple is highest at maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. output voltage programming the resistive divider allows the fb pin to sense a fraction of the output voltage as shown in figure 4. ) r2 r1 (1 v v ref out + = figure 4. setting the output voltage where v ref is the internal reference voltage (0.6v typ.) for adjustable voltage mode, the output voltage is set by an external resistive divider according to the following equation : efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. efficiency can be expressed as : efficiency = 100% ? (l1+ l2+ l3+ ...) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses : vin quiescent current and i 2 r losses. the vin quiescent current loss dominates the efficiency loss at very low load currents whereas the i 2 r loss dominates the efficiency loss at medium to high load currents. in a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1. the vin quiescent current appears due to two factors including : the dc bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. the gate charge current results from switching the gate capacitance of the internal power mosfet switches. each time the gate is switched from high to low to high again, a packet of charge q moves from v in to ground. the resulting q/ t is the current out of v in that is typically larger than the dc bias current. in continuous mode, i gatechg = f(q t +q b ) where q t and q b are the gate charges of the internal top and bottom switches. both the dc bias and gate charge losses are proportional to v in and thus their effects will be more pronounced at higher supply voltages. rt8010/a gnd fb r1 r2 v out
rt8010/a 12 ds8010/a-02 march 2007 www.richtek.com checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load (esr), where esr is the effective series resistance of c out . i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. layout considerations follow the pcb layout guidelines for optimal performance of rt8010/a. ` for the main current paths as indicated in bold lines in figure 6, keep their traces short and wide. ` put the input capacitor as close as possible to the device pins (vin and gnd). ` lx node is with high frequency voltage swing and should be kept small area. keep analog components away from lx node to prevent stray capacitive noise pick-up. ` connect feedback network behind the output capacitors. keep the loop area small. place the feedback components near the rt8010/a. 2. i 2 r losses are calculated from the resistances of the internal switches, r sw and external inductor r l . in continuous mode, the average output current flowing through inductor l is ? chopped ? between the main switch and the synchronous switch. thus, the series resistance looking into the lx pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows : r sw = r ds(on)top x dc + r ds(on)bot x (1 ? dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus, to obtain i 2 r losses, simply add r sw to r l and multiply the result by the square of the average output current. other losses including c in and c out esr dissipative losses and inductor core losses generally account for less than 2% of the total loss. thermal considerations the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = ( t j(max) - t a ) / ja where t j(max) is the maximum operation junction temperature, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification of rt8010/a dc/dc converter, where t j(max) is the maximum junction temperature of the die and t a is the maximum ambient temperature. the junction to ambient thermal resistance ja is layout dependent. for wdfn-6l 2x2 packages, the thermal resistance ja is 165 c/w on the standard jedec 51-7 four layers thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c ? 25 c) / 165 c/w = 0.606w for wdfn-6l 2x2 packages the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . for rt8010/a packages, the figure 5 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. figure 5. derating curves for rt8010/a package 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 25 50 75 100 125 ambient temperature maximum power dissipation (w) four layers pcb wdfn-6l 2x2 ( c) wqfn-16l 3x3
rt8010/a 13 ds8010/a-02 march 2007 www.richtek.com ` connect all analog grounds to a command node and then connect the command node to the power ground behind the output capacitors. ` an example of 2-layer pcb layout is shown in figure 7 to figure 8 for reference. figure 6. evb schematic lx gnd rt8010/a en fb/vout l1 c3 v in v out c1 r1 r2 vin v in 3 2 5 4 6 c2 nc 1 r3 figure 7. top layer figure 8. bottom layer table 1. recommended inductors table 2. recommended capacitors for c in and c out supplier inductance (uh) current rating (ma) dcr (m ? ) dimensions (mm) series taiyo yuden 2.2 1480 60 3.00 x 3.00 x 1.50 nr 3015 gotrend 2.2 1500 58 3.85 x 3.85 x 1.80 gtsd32 sumida 2.2 1500 75 4.50 x 3.20 x 1.55 cdrh2d14 sumida 4.7 1000 135 4.50 x 3.20 x 1.55 cdrh2d14 taiyo yuden 4.7 1020 120 3.00 x 3.00 x 1.50 nr 3015 gotrend 4.7 1100 146 3.85 x 3.85 x 1.80 gtsd32 supplier capacitance (uf) package part number tdk 4.7 603 c1608jb0j475m murata 4.7 603 grm188r60j475ke19 taiyo yuden 4.7 603 jmk107bj475ra taiyo yuden 10 603 jmk107bj106ma tdk 10 805 c2012jb0j106m murata 10 805 grm219r60j106me19 murata 10 805 grm219r60j106ke19 taiyo yuden 10 805 jmk212bj106rd
rt8010/a 14 ds8010/a-02 march 2007 www.richtek.com outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.200 0.350 0.008 0.014 d 1.950 2.050 0.077 0.081 d2 1.000 1.450 0.039 0.057 e 1.950 2.050 0.077 0.081 e2 0.500 0.850 0.020 0.033 e 0.650 0.026 l 0.300 0.400 0.012 0.016 w-type 6l dfn 2x2 package d 1 e a3 a a1 e b l d2 e2 see detail a 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options
rt8010/a 15 ds8010/a-02 march 2007 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 8f, no. 137, lane 235, paochiao road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)89191466 fax: (8862)89191465 email: marketing@richtek.com a a1 a3 d e 1 d2 e2 l b e see detail a dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 2.950 3.050 0.116 0.120 d2 1.300 1.750 0.051 0.069 e 2.950 3.050 0.116 0.120 e2 1.300 1.750 0.051 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 16l qfn 3x3 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2

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